GitHub - vincentchu12/VerilogUARTModule: Verilog UART Module with Tx/Rx Fifo, supports up to 115200 bps

Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
UART.cache/wt		UART.cache/wt
UART.hw		UART.hw
UART.ip_user_files		UART.ip_user_files
UART.runs		UART.runs
UART.sim/sim_1/behav/xsim		UART.sim/sim_1/behav/xsim
UART.srcs		UART.srcs
UART.xpr		UART.xpr